1. Field of the Invention
The present invention relates in general to output buffers for semiconductor devices, and more particularly to a noise attenuation output buffer for effectively attenuating noise in output data.
2. Description of the Prior Art
Generally, a noise attenuation output buffer is mainly used in a semiconductor device to attenuate noise in output data. In the noise attenuation output buffer, noise is generated when a pull-down N-channel Metal-Oxide-Silicon (referred to hereinafter as NMOS) transistor is changed from its OFF state to its ON state. In order to reduce such noise, a current path is formed between a gate terminal of the pull-down NMOS transistor and a ground terminal at a time point that a signal is applied to turn on the pull-down NMOS transistor. The formation of current path has the effect of absorbing noise being instantaneously generated. Such a conventional noise attenuation output buffer will hereinafter be described with reference to FIGS. 1 to 2B.
Referring to FIG. 1, there is shown a detailed circuit diagram of a conventional noise attenuation output buffer. As shown in this drawing, the conventional noise attenuation output buffer comprises a NOR gate 1 for NORing an enable signal and input data, and a pull-up/down driver 4 for performing a pull-up operation in response to the input data and a pull-down operation in response to an output signal from the NOR gate 1 to provide output data. The pull-up/down driver 4 includes a pull-up P-channel Metal-Oxide-Silicon (referred to hereinafter as PMOS) transistor and a pull-down NMOS transistor. The pull-up PMOS transistor has a gate terminal for inputting an inverted one of the input data. The pull-down NMOS transistor has a gate terminal for inputting the output signal from the NOR gate 1.
The conventional noise attenuation output buffer further comprises a noise attenuation controller 2 for outputting a noise attenuation signal through a noise attenuation signal output node in response to a drive voltage Vcc, the input data and the output signal from the NOR gate 1. When the input data is "0" or low in logic and noise is increased as the drive voltage Vcc exceeds a normal value of, for example, 5 V, the noise attenuation controller 2 transfers the drive voltage Vcc to the noise attenuation signal output node. As a result, the noise attenuation signal on the noise attenuation signal output node becomes high in logic. On the contrary, when the input data is "1" or high in logic, the noise attenuation controller 2 transfers the output signal from the NOR gate 1 to the noise attenuation signal output node. As a result, the noise attenuation signal on the noise attenuation signal output node becomes low in logic.
The conventional noise attenuation output buffer further comprises a noise attenuator 3 for performing a switching operation in response to the noise attenuation signal from the noise attenuation controller 2 and the output data from the pull-up/down driver 4 to form a current path between an output terminal of the NOR gate 1 and a ground terminal. When the noise attenuation signal from the noise attenuation controller 2 and the output data from the pull-up/down driver 4 are both high in logic, the current path is formed between the output terminal of the NOR gate 1 and the ground terminal, thereby absorbing noise generated when the pull-down NMOS transistor in the pull-up/down driver 4 is turned on.
The noise attenuation controller 2 includes an NMOS transistor, a first PMOS transistor and three second PMOS transistors. The NMOS transistor is connected between the output terminal of the NOR gate 1 and the noise attenuation signal output node and has a gate terminal for inputting the input data. The first PMOS transistor has a gate terminal for inputting the input data and a source terminal for inputting the drive voltage Vcc. The three second PMOS transistors are connected in series between a drain terminal of the first PMOS transistor and the noise attenuation signal output node. Each of the three second PMOS transistors has a gate terminal and a drain terminal connected to each other. The three second PMOS transistors are turned on with their sources applied with the drive voltage Vcc exceeding the normal value of 5 V. As a result, when the input data is changed from high to low in logic and noise is increased as the drive voltage Vcc exceeds the normal value of 5 V, the three second PMOS transistors transfer the drive voltage Vcc to the noise attenuation signal output node to generate the noise attenuation signal of high logic.
The noise attenuator 3 includes first and second NMOS transistors. The first NMOS transistor has a gate for inputting the noise attenuation signal from the noise attenuation controller 2 and a drain terminal connected to the output terminal of the NOR gate 1. The second NMOS transistor has a gate terminal for inputting the output data from the pull-up/down driver 4, a drain terminal connected to a source terminal of the first NMOS transistor and a source terminal connected to the ground terminal. When the noise attenuation signal from the noise attenuation controller 2 and the output data from the pull-up/down driver 4 are both high in logic, the first and second NMOS transistors are turned on to form the current path between the output terminal of the NOR gate 1 and the ground terminal. On the contrary, when the output data from the pull-up/down driver 4 is low in logic or the noise attenuation signal from the noise attenuation controller 2 is low in logic under the effect of little noise, the first or second NMOS transistor is turned off to remove the current path between the output terminal of the NOR gate 1 and the ground terminal.
FIG. 2A is a waveform diagram illustrating voltage-time characteristics of the components in FIG. 1 and FIG. 2B is a waveform diagram illustrating a current-time characteristic of the pull-down NMOS transistor in FIG. 1. In FIG. 2A, a solid line indicates a voltage waveform of the input data, a dotted and dashed line indicates a voltage waveform of the output signal from the noise attenuation controller 2, a phantom line indicates a voltage waveform of the output signal from the NOR gate 1 and a dotted line indicates a voltage waveform of the output data from the pull-up/down driver 4. As seen from these drawings, when the input data is changed from high to low in logic, the output signal from the NOR gate 1 begins to make a transition before the output signal from the noise attenuation controller 2 goes from low to high in logic to completely turn on the noise attenuator 3. For this reason, noise cannot be effectively attenuated. Namely, an increase rate dI/dt of current flowing through the pull-down NMOS transistor which is the main factor of generating noise becomes considerably large due to the earlier transition of the output signal from the NOR gate 1. In this case, the increase rate dI/dt of current flowing through the pull-down NMOS transistor iS typically 12.5.times.10.sup.6. Furthermore, the ineffective ON timing of the noise attenuator 3 results in extension in the voltage waveform of the output signal from the NOR gate 1 and the current waveform of the pull-down NMOS transistor, reducing the actual data output speed.
In result, the conventional noise attenuation output buffer has the disadvantage that it cannot effectively attenuate noise in the output data because of the ineffective ON timing of the noise attenuator. Also, the ineffective ON timing of the noise attenuator results in a degradation in the data output speed.